PIC16C54C-04/SO【PDF 131/194 页】IC MCU OTP 512X12 18SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3886

127页 128页 129页 130页 [131页]132页 133页 134页 135页

2002 Microchip Technology Inc.

Preliminary

DS30453D-page 39

PIC16C5X

8.1

Using Timer0 with an External

Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock require-

ment is due to internal phase clock (TOSC) synchroniza-

tion. Also, there is a delay in the actual incrementing of

Timer0 after synchronization.

8.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 8-5).

Therefore, it is necessary for T0CKI to be high for at

least 2TOSC (and a small RC delay of 20 ns) and low for

at least 2TOSC (and a small RC delay of 20 ns). Refer

to the electrical specification of the desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type pres-

caler so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4TOSC (and a small RC delay of 40 ns) divided by

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pulse width requirement of 10 ns. Refer to param-

eters 40, 41 and 42 in the electrical specification of the

desired device.

8.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0 mod-

ule is actually incremented. Figure 8-5 shows the delay

from the external clock edge to the timer incrementing.

FIGURE 8-5:

TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or

Q3 Q4

Timer0

T0 + 1

T0 + 2

Small pulse

misses sampling

External Clock/Prescaler

Output After Sampling

(2)

Prescaler Output (1)

(3)

Note 1: External clock if no prescaler selected, prescaler output otherwise.

2: The arrows indicate the points in time where sampling occurs.

3: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc (duration of Q = Tosc). Therefore,

the error in measuring the interval between two edges on Timer0 input =

± 4Tosc max.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式